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Formal Verification Engineer

at Intel in Springfield, Illinois, United States

Job Description

Job Description

The world is transforming – and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on Earth. We believe that developing these technologies takes a team of exceptionally talented individuals who work together to visualize, innovate, and make the future of computing possible. If you are excited about advanced development of breakthrough technologies for future-generation CPU cores, we invite you to join us to do something wonderful. As a member of a CPU Core development team of pre-silicon verification engineers, you will verify new and existing features for Intel’s next generation CPU IP, resulting in a bug-free final design. You will be responsible for exhaustively validating the RTL implementation of new architecture and microarchitecture capabilities, using a combination of unit- and top-level test environments.

Responsibilities include but not limited to:

Collaborate with architect hardware engineers and microcode engineers to understand the new features being implemented.

Read and interpret technical specs

Select units for suitable for Formal, create high quality technical documentation such as Formal test plans.

Create formal testbenches to constrain the design environment

Write additional assertions to stress the design

Debug and root-cause failing assertions and environment constraints

Fix all identified failures in the design and in the Formal testbench

Apply abstraction techniques to combat the state explosion problem and go deeper into the design.

Qualifications

This is an entry level position and will be compensated accordingly . You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research and relevant previous job and/or internship experience.

Minimum Qualifications:

Master’s or PhD degree in electrical or computer engineering or any STEM related degree

3+ months of experience in one or more of the following:

CPU or ASIC verification

Experience with SVA

Experience with Verilog, System Verilog

Either RTL design experience or experience using one of the existing Formal tools (JG/VCF ….)

Experience with debugging RTL code using either simulation tools or Formal tools

Preferred Experience:

Bachelors in electrical or computer engineering or any STEM related degree with 3+ years of industry experience

Projects or internship in CPU or ASIC verification and functional modeling

Experience with scripting languages like Python/TCL is a plus.

Exposure to formal verification and related tools

Inside this Business Group

The Advanced Architecture Development Group (AADG) is a CPU Core development team in Portland, Oregon. If you are excited about advanced development of breakthrough technologies for future-generation CPU cores, please join us. We believe that developing these technologies takes a team of exceptionally talented individuals who work together to visualize, innovate, and make the future of computing possible. Join us to do something wonderful!

Other Locations

US, TX, Austin; US, CA, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as

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Job Posting: JC251790525

Posted On: Nov 30, 2023

Updated On: Dec 14, 2023

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