at Intel in Springfield, Illinois, United States
The X-Chip Integration team is looking for an SoC Design Engineer to join Design Enablement (DE) team in Technology Development (TD) organization. The charter of the team is to develop physical design methodology for Test Chip lead vehicles which are primarily used for Intel’s next generation process development and high-volume certification.
As a SoC Design Engineer, your responsibilities will include but not be limited to:
+ Developing layout design methodology and productivity automation for cutting edge process nodes.
+ Working closely with LTD Process Engineers to define critical Design features that needs to be exercised in the early lead vehicle test chips.
+ Establishing, orchestrating, overseeing, and maintaining hierarchical layout design specifications for correct-by-construction integration.
+ Building and executing tactical plans to converge hierarchical SOC layout design against aggressive schedule requirements.
+ Orchestrating mock full-chip assembly and tape-ins in preparation for the real thing and to provide package and tape-out partners with representative data for planning and product prep.
+ Building and supporting tools, capabilities, methods, and work models for global layout design and convergence.
+ Driving all aspects of physical design convergence, including preparing layout hierarchy for design tape-in, debugging and resolving issues uncovered by verification tools.
+ Working with tool/flow owners and vendors for ongoing tool/methodology improvement.
+ Success in this job requires working closely with Engineering, DAs, and manufacturing partners with a goal to robustly tape-in a complex multi-hierarchical SOC within hours of final block completion.
The ideal candidate should exhibit the following behavioral traits:
+ Verbal and written communication skills.
+ Ability to work well both autonomously and in an intensive, cooperative team environment.
+ Exhibiting interest in Layout design.
+ Motivation to continuously learn and drive to push improved layout productivity and efficiency.
This is a remote internship with a length of 6+ months.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Candidate must be actively pursuing a MS degree in Electrical Engineering or Computer Engineering.
6+ months of experience in the following:
- VLSI design and layout design.
- Scripting or programming languages, such Perl, Python, TCL, Skill, etc.
6+ months of experience in the following:
- Familiarity with Candance Virtuoso, Synopsys Fusion Compiler (FC), Synopsys design planning, Synopsys ICV or Calibre rule decks.
Inside this Business Group
As the world’s largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art — from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)
Annual Salary Range for jobs which could be performed in US, Colorado, New York, Washington, California: $63,000.00-$166,000.00
*Salary range dependent on a number of factors including location and experience
This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. This role may also be available as our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.